1. Field of the Invention
The present invention relates to a semiconductor device equipped with a jitter detection circuit and a jitter detection method thereof.
2. Description of Related Art
In recent years, as semiconductor components have gotten more miniaturized, an integrated circuit comprising those semiconductor components have been becoming larger in scale. Therefore, some of integrated circuits of recent years have a Phase-Locked Loop (PLL) circuit embedded within them. This PLL circuit is used not only to generate a clock signal used in the chip, but also to match the clock with the phase of an external clock.
Since this PLL circuit is a feedback circuit, the clock frequency can be varied depending on the stability. Jitter is one of these fluctuation widths as the clock phase is changed. When the fluctuation width of jitter is too large, it affects the operational stability of the integrated circuit which is synchronizing with the clock. Japanese Unexamined patent publication Nos. 10-267999 and 2003-179142 disclose techniques for measuring jitter in an integrated circuit having a PLL circuit.
In the technique disclosed in Japanese Unexamined patent publication No. 10-267999, a test input signal is input while varying the phase of the signal. Then, the test signal is latched in synchronization with a receive clock and output. The fluctuation width is measured by comparing the output signal with an expected output value.
The technique disclosed in Japanese Unexamined patent publication No. 2003-179142 introduces an embedded oscillation circuit called “window clock oscillation circuit”. Using a delay circuit for the falling edge of the window clock signal to change as appropriate the time period during which clock cycles output from the PLL circuit is counted, jitter is examined based on the number of the falling edges of the clock signal output from the PLL circuit.
However, in the technique disclosed in Japanese Unexamined patent publication No. 10-267999, there is a problem that since it includes jitter caused by a test board extending to the PLL embedded circuit, it cannot accurately measure jitter caused by the embedded PLL circuit itself. Furthermore, in the technique disclosed in Japanese Unexamined patent publication No. 2003-179142, the characteristics of the delay circuit contained in the internal circuit varies depending on voltage, temperature, and the like. Consequently, the jitter measurement may be varied depending on the surrounding environment or the like, and therefore it is difficult to accurately measure jitter. In addition, in a circuit disclosed in Japanese Unexamined patent publication No. 2003-179142 or similar circuit, since the circuit itself is complicated, it increases the circuit scale.
In a conventional Jitter detection circuit, it is difficult to accurately measure the fluctuation rate of jitter with simple circuitry.